Raspberry Pi /RP2350 /I2C0 /IC_STATUS

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Interpret as IC_STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INACTIVE)ACTIVITY 0 (FULL)TFNF 0 (NON_EMPTY)TFE 0 (EMPTY)RFNE 0 (NOT_FULL)RFF 0 (IDLE)MST_ACTIVITY 0 (IDLE)SLV_ACTIVITY

SLV_ACTIVITY=IDLE, ACTIVITY=INACTIVE, RFNE=EMPTY, TFNF=FULL, TFE=NON_EMPTY, MST_ACTIVITY=IDLE, RFF=NOT_FULL

Description

I2C Status Register

This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.

When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0

Fields

ACTIVITY

I2C Activity Status. Reset value: 0x0

0 (INACTIVE): I2C is idle

1 (ACTIVE): I2C is active

TFNF

Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1

0 (FULL): Tx FIFO is full

1 (NOT_FULL): Tx FIFO not full

TFE

Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1

0 (NON_EMPTY): Tx FIFO not empty

1 (EMPTY): Tx FIFO is empty

RFNE

Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0

0 (EMPTY): Rx FIFO is empty

1 (NOT_EMPTY): Rx FIFO not empty

RFF

Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0

0 (NOT_FULL): Rx FIFO not full

1 (FULL): Rx FIFO is full

MST_ACTIVITY

Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.

Reset value: 0x0

0 (IDLE): Master is idle

1 (ACTIVE): Master not idle

SLV_ACTIVITY

Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0

0 (IDLE): Slave is idle

1 (ACTIVE): Slave not idle

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